The present disclosure relates to a jitter of a clock signal, and more particularly, to a circuit for and a method of measuring a jitter of a clock signal.
A digital circuit may operate in synchronization with a clock signal. For example, the digital circuit may include a plurality of flip-flops, and each of the flip-flops may operate in response to an edge of a clock signal. In addition, function blocks that are included in the digital circuit and operate in synchronization with a clock signal may have different operating frequencies, and thus, a plurality of clock signals having various frequencies may be generated.
A clock signal may have a jitter, and the performance of a function block may be limited by the jitter of the clock signal due to a design made in consideration of the jitter of the clock signal. The jitter of the clock signal may differ between dies (or, chips) due to variations in a semiconductor manufacturing process, may vary depending on the temperature of a digital circuit or a voltage applied to the digital circuit, and may depend on the performance a phase locked loop (PLL) generating the clock signal.